The present invention relates to semiconductor devices and methods for fabricating the same with respect to a structure for drawing the potential of an upper electrode in a dielectric memory.
Ferroelectric memories having small capacities of 1 to 64 kbits using a planer or stacked structures have begun to be manufactured. In recent years, development of ferroelectric memories having three-dimensional stacked structures utilizing not only flat portions but also side portions of ferroelectric films has started. In a ferroelectric memory having a three-dimensional stacked structure, a contact plug electrically connected to a semiconductor substrate is placed immediately under a lower electrode so that a cell size is reduced and the integration degree is enhanced. In addition, a capacitive dielectric film is formed along a step so that the surface area of the capacitive dielectric film increases and a sufficient capacity is obtained. In this field, various cell structures of DRAMs have been proposed prior to ferroelectric memories.
First, a semiconductor device according to a first conventional example will be described with reference to FIG. 24 (see, for example, reference 1: Japanese Unexamined Patent Publication (Kokai) No. 2002-83880 (FIG. 1)).
FIG. 24 is a cross-sectional view illustrating a semiconductor device including a capacitor with a double-sided cylinder structure.
As shown in FIG. 24, isolation regions 11 are provided in a memory cell array region A1 and a peripheral region A2 of a silicon substrate 10. A gate insulating film 12 is formed on the silicon substrate 10. Gate electrodes 13 are formed on the gate insulating film 12. A doped layer (not shown) to be source/drain regions is selectively defined in a surface portion of the silicon substrate 10. In this manner, MOS transistors are formed. A first silicon nitride film 14 is formed over the silicon substrate 10 to cover the MOS transistors. A first interlayer insulating film 15 and a first silicon oxide film 16 are formed in this order over the first silicon nitride film 14. In a region which is not shown, interconnects 17 connected to drain regions of cell transistors are provided in the first interlayer insulating film 15 in the memory cell array region A1. Interconnects 17 connected to drain regions of the MOS transistors are provided in the peripheral region A2.
Contact plugs 18 connected to source regions of the MOS transistors are formed in the first silicon nitride film 14, the first interlayer insulating film 15 and the first silicon oxide film 16. A multilayer interlayer insulating film made of a second silicon nitride film 19, a second silicon oxide film 20 and a third silicon nitride film 21 is formed on the first silicon oxide film 16. Cylindrical holes 22 in which the first silicon oxide film 16 and the contact plugs 18 are exposed are formed in the multilayer interlayer insulating film. Each of the holes 22 is provided for an associated one of the contact plugs 18. A liner material 23 is provided on the inner wall and bottom of each of the holes 22.
In each of the holes 22, a lower electrode 24 that constitutes a double-sided cylinder capacitor in the shape of a cylinder and has a given thickness is formed on the bottom of the hole 22. The lower electrode 24 is electrically connected to an associated one of the contact plugs 18 via the liner material 23. Capacitive insulating films 25 are provided on the lower electrodes 24. Upper electrodes 26 are provided on the capacitive dielectric films 25. In this manner, double-sided cylinder stacked capacitors are formed.
A second interlayer insulating film 27 is formed on the upper electrodes 26. A contact hole 28 is formed through the second interlayer insulating film 27 to reach one of the upper electrodes 26. A metal interconnect layer 29 is provided so that the contact hole 28 is filled therewith. A third interlayer insulating film 30 is provided on the second interlayer insulating film 27. In this manner, a DRAM is formed.
In the three-dimensional structure of the DRAM described above, the potential of the upper electrode 26 is drawn from an upper portion via the contact plug directly connecting the upper electrode 26 to the interconnect 29.
Now, a semiconductor device according to a second conventional example will be described with reference to FIG. 25 (see, for example, reference 2: U.S. Pat. No. 5,567,636 (FIG. 15)).
FIG. 25 is a cross-sectional view illustrating a semiconductor device according to the second conventional example.
As shown in FIG. 25, isolation regions 51 and a doped layer 52 are formed in a silicon substrate 50. An interlayer insulating film 53 is provided over the silicon substrate 50, the isolation regions 51 and the doped layer 52. Contact plugs 54 are formed through the interlayer insulating film 53 connected at their lower ends to the doped layer 52. Lower electrodes 55 and ferroelectric films 56 are stacked in this order over the respective contact plugs 54. Sidewalls 58 for preventing short-circuits between the lower electrodes 55 and an upper electrode 57, which will be described later, are formed on the side surfaces of the lower electrodes 55 and the ferroelectric films 56. As shown in FIG. 25, an opening 59 is formed in one of the ferroelectric films 55 such that the upper surface of an associated one of the lower electrodes 55 is exposed in the opening 59. On the interlayer insulating film 53, an upper electrode 57 is formed to cover the lower electrodes 55, the ferroelectric films 56 and the sidewalls 58. In this manner, in the semiconductor device of the second conventional example shown in FIG. 25, the potential of the upper electrode 57 is not directly drawn to an upper portion but is drawn via the lower electrode 55.
However, as described for the first conventional example, when the structure in which the lower end of the contact plug from the interconnect is connected to the upper surface of the upper electrode is applied to a ferroelectric memory so as to draw the potentials of the upper electrode, the following problem arises.
That is, a ferroelectric film serving as a capacitive dielectric film constituting a ferroelectric memory is made of a metal oxide, typified by SrBi2Ta2O9-based bismuth layer-structures or PbZrO3-based perovskite crystal structures. These metal oxides are readily reduced when exposed to a reducing atmosphere, thus causing a problem of deterioration of properties of the ferroelectric film.
To prevent deterioration of properties of a ferroelectric film, a method using smaller amount of hydrogen in semiconductor processing conditions after formation of the ferroelectric film and a method of covering a ferroelectric capacitor with a hydrogen barrier film are generally adopted. In recent years, the latter method has been mainly adopted. This is because processes inevitably using hydrogen have appeared in semiconductor processing such as WCVD or recovery of Tr to meet increasing demand for miniaturization of semiconductor devices.
In the structure of the first conventional example in which ferroelectric capacitors are covered with a hydrogen barrier film, since the contact plug from the interconnect is connected to the upper electrode as described above, the contact plug has to be formed through a hydrogen barrier film provided over the upper electrode. Accordingly, entering of hydrogen into the ferroelectric films via the contact plug is unavoidable. Even if a hydrogen barrier material is used as a material with which the contact plug is filled, influences by hydrogen (e.g., CH3 used for an etching gas) during formation of the contact hole cannot be avoided.
In the second conventional example, the structure in which a portion for drawing the potential of the upper electrode is connected to the doped layer via the opening of the ferroelectric film is disclosed. However, a problem arising when the ferroelectric memory has a three-dimensional stacked structure typified by a tapered structure is not taken into consideration.
Specifically, if the ferroelectric memory has a three-dimensional stacked structure, this structure makes the ferroelectric film formed along steps, so that the longitudinal distance between the upper electrode and lower electrodes or between the upper electrode and the storage node contact plugs is relatively large. Accordingly, problems such as deterioration of step coverage of the upper electrode deteriorates, difficulty in forming an opening having a high aspect ratio itself, and more difficulty in forming such an opening in a multilayer film arise. Therefore, if the ferroelectric memory has a three-dimensional stacked structure, it is difficult to achieve a structure in which the potential of the upper electrode is drawn to the doped layer via the opening of the ferroelectric film. In particular, with an advanced high-aspect-ratio structure that is a feature of a ferroelectric memory with a three-dimensional stacked structure, invention of a contact structure for a three-dimensional stacked structure in which a contact yield is taken into consideration becomes urgently imperative.
In the second conventional example, however, neither application of the structure in which the portion for drawing the potential of the upper electrode is connected to the doped layer via the opening in the ferroelectric film to a ferroelectric memory with a three-dimensional stacked structure nor application thereof to the structure in which the ferroelectric capacitor is covered with the hydrogen barrier film is disclosed.